In general, in a memory cell array of a semiconductor memory device, for example, a Dynamic Random Access Memory (DRAM) semiconductor memory device, word lines and bit lines are arranged to perpendicularly intersect each other. Through a switching circuit, the bit lines are connected to I/O lines through which data is input or output. Each memory cell is typically arranged at one of the intersections of the bit lines and word lines. As the storage capacity of a semiconductor memory device increases, the memory cells and the peripheral circuit that controls data to be written to or to be read from the memory cells have generally become more highly integrated.
For high speed operation of the I/O lines, the I/O lines embedded in the semiconductor memory device may have a hierarchical I/O line structure in which the I/O lines are divided into local I/O lines and global I/O lines. Likewise, in order to reduce signal delays due to the resistance of poly-silicon used as word lines, a hierarchical word line structure in which word lines are divided into main word lines and sub-word lines may have also been widely used.
Conventionally, the number of sub-arrays arranged in length on the matrix of a memory cell array is 16. Recently, however, in order to reduce the size of a chip while maintaining the same storage capacity, the number of sub-arrays arranged in length has been reduced to 14 or 12.
FIG. 1 is a partial layout diagram of a semiconductor memory device having a conventional hierarchical I/O line structure. Referring to FIG. 1, the semiconductor memory device 10 has a memory cell array containing a plurality of sub-arrays 11, a column decoder 12 and a row decoder 13. A sub-array 11 has a plurality of memory cells.
The memory cell array may be divided into 96 (=12×8) sub-arrays 11 by bit line sense amplifier areas 14 and sub-word line driver areas 15. The bit line sense amplifier areas 14 are repeatedly arranged in the column direction, while the sub-word line driver areas 15 are repeatedly arranged in the row direction. In a bit line sense amplifier area 14, a bit line sense amplifier (not shown) is arranged, while in a sub-word line driver area 15 a sub-word line driver (not shown) driving a sub-word line is arranged.
The semiconductor memory device 10 has a hierarchical word line structure. That is, a plurality of Main Word Lines (MWLs) are connected to the row decoder 13, crossing over 12 of the sub-arrays 11 in the column direction, and each of a plurality of sub-word lines (not shown) which are connected to the MWLs through a predetermined driver are arranged on a sub-array 11. In response to a row address, the row decoder 13 selects and activates MWLs. MWLs are also referred to as Normal Word Lines (NWLs).
A plurality of Column Selection Lines (CSLs) are connected to the column decoder 12, crossing over 8 of the sub-arrays 11 in the row direction. The column decoder 12 selects and activates the CSLs.
The semiconductor memory device 10 has a hierarchical I/O line structure. For each 3 of the sub-arrays 11, a pair of Local I/O lines (LIO) are provided. Usually, as shown in FIG. 1, a LIO is divided into 4 segments or a multiple of 4 segments. After being divided in conjunction areas where the bit line sense amplifier areas 14 and the sub-word line driver areas 15 intersect, the LIOs are repeatedly arranged in the column direction. A LIO that is arranged in a bit line sense amplifier area 14 is commonly used by the two sub-arrays 11 arranged one at either side of the LIO. A pair of Global I/O lines (GIO) are connected to the LIOs through switching circuits, and for each 3 of the sub-arrays 11 arranged in the column direction, a GIO is repeatedly arranged on a sub-word line driver area. Each of the switching circuits is arranged at an intersection area 16 where a GIO and the LIOs intersect each other.
FIG. 2 is a detailed diagram of region A in which pairs of local I/O lines shown in FIG. 1 are divided.
The sub-arrays 11 are divided by the Bit Line Sense Amplifier areas (BL S/A) and Sub-Word line Driver areas (SWD). On each of the sub-arrays 11, a plurality of Sub-Word Lines (SWL) and a plurality of pairs of Bit Lines (BL) are arranged intersecting each other. A memory cell is arranged at intersection areas where a SWL and a BL intersect each other. A sub-word line driver (not shown) driving a SWL is arranged in a SWD, and a bit line sense amplifier that is connected to a BL is arranged in a BL S/A.
An LIO is divided in a conjunction area (CONJUNCTION) and is arranged in a BL S/A, perpendicularly intersecting BLs. In the conjunction area, a control circuit is provided that controls the SWD and the BL S/A.
However, when the size of a chip is reduced while maintaining the same data storage capacity, for example, when 10 sub-arrays having relatively larger data storage capacity than the sub-arrays 11 of the conventional semiconductor memory device are arranged in the column direction such that the chip size is reduced, it may be necessary to divide the LIO, not in the conjunction area, but in the BL S/A. However, since the area needed to divide the LIO on the BL S/A is typically too small, the LIO typically cannot be divided in the BL S/A, and it may be difficult to implement a hierarchical I/O line structure.